\doxysection{C\+:/\+Users/\+ASUS/\+Desktop/dm-\/ctrl\+H7-\/balance-\/9025test/\+Drivers/\+STM32\+H7xx\+\_\+\+HAL\+\_\+\+Driver/\+Inc/stm32h7xx\+\_\+hal\+\_\+i2c.h File Reference}
\hypertarget{stm32h7xx__hal__i2c_8h}{}\label{stm32h7xx__hal__i2c_8h}\index{C:/Users/ASUS/Desktop/dm-\/ctrlH7-\/balance-\/9025test/Drivers/STM32H7xx\_HAL\_Driver/Inc/stm32h7xx\_hal\_i2c.h@{C:/Users/ASUS/Desktop/dm-\/ctrlH7-\/balance-\/9025test/Drivers/STM32H7xx\_HAL\_Driver/Inc/stm32h7xx\_hal\_i2c.h}}


Header file of I2C HAL module.  


{\ttfamily \#include "{}stm32h7xx\+\_\+hal\+\_\+def.\+h"{}}\newline
{\ttfamily \#include "{}stm32h7xx\+\_\+hal\+\_\+i2c\+\_\+ex.\+h"{}}\newline
\doxysubsubsection*{Classes}
\begin{DoxyCompactItemize}
\item 
struct \mbox{\hyperlink{struct_i2_c___init_type_def}{I2\+C\+\_\+\+Init\+Type\+Def}}
\item 
struct \mbox{\hyperlink{struct_____i2_c___handle_type_def}{\+\_\+\+\_\+\+I2\+C\+\_\+\+Handle\+Type\+Def}}
\end{DoxyCompactItemize}
\doxysubsubsection*{Macros}
\begin{DoxyCompactItemize}
\item 
\#define \mbox{\hyperlink{group___i2_c___error___code__definition_ga0b8ca289091d942032c89484b6211d0d}{HAL\+\_\+\+I2\+C\+\_\+\+ERROR\+\_\+\+NONE}}~(0x00000000U)
\item 
\#define \mbox{\hyperlink{group___i2_c___error___code__definition_gab9f6e39431ee764ada50fd63f0ad2fbf}{HAL\+\_\+\+I2\+C\+\_\+\+ERROR\+\_\+\+BERR}}~(0x00000001U)
\item 
\#define \mbox{\hyperlink{group___i2_c___error___code__definition_ga048b36222884bfe80ce2d37fa868690b}{HAL\+\_\+\+I2\+C\+\_\+\+ERROR\+\_\+\+ARLO}}~(0x00000002U)
\item 
\#define \mbox{\hyperlink{group___i2_c___error___code__definition_gad1cc236ad6ba5cafe66aecb0dbedc65a}{HAL\+\_\+\+I2\+C\+\_\+\+ERROR\+\_\+\+AF}}~(0x00000004U)
\item 
\#define \mbox{\hyperlink{group___i2_c___error___code__definition_ga38d8f9beb4c681eba786f6154d4f594a}{HAL\+\_\+\+I2\+C\+\_\+\+ERROR\+\_\+\+OVR}}~(0x00000008U)
\item 
\#define \mbox{\hyperlink{group___i2_c___error___code__definition_gae1091e9e82dcfcfef247b214a11c9db3}{HAL\+\_\+\+I2\+C\+\_\+\+ERROR\+\_\+\+DMA}}~(0x00000010U)
\item 
\#define \mbox{\hyperlink{group___i2_c___error___code__definition_gaeb3bedf36d78ddf3284a68494ab9d089}{HAL\+\_\+\+I2\+C\+\_\+\+ERROR\+\_\+\+TIMEOUT}}~(0x00000020U)
\item 
\#define \mbox{\hyperlink{group___i2_c___error___code__definition_ga98027ff2d2fda2c793b07168ded747a4}{HAL\+\_\+\+I2\+C\+\_\+\+ERROR\+\_\+\+SIZE}}~(0x00000040U)
\item 
\#define \mbox{\hyperlink{group___i2_c___error___code__definition_gacb922e1386469dce306f548cfd5c1277}{HAL\+\_\+\+I2\+C\+\_\+\+ERROR\+\_\+\+DMA\+\_\+\+PARAM}}~(0x00000080U)
\item 
\#define \mbox{\hyperlink{group___i2_c___error___code__definition_gac2d3acb9e918667866677dc6b3e92cd8}{HAL\+\_\+\+I2\+C\+\_\+\+ERROR\+\_\+\+INVALID\+\_\+\+PARAM}}~(0x00000200U)
\item 
\#define {\bfseries I2\+C\+\_\+\+FIRST\+\_\+\+FRAME}~((uint32\+\_\+t)I2\+C\+\_\+\+SOFTEND\+\_\+\+MODE)
\item 
\#define {\bfseries I2\+C\+\_\+\+FIRST\+\_\+\+AND\+\_\+\+NEXT\+\_\+\+FRAME}~((uint32\+\_\+t)(I2\+C\+\_\+\+RELOAD\+\_\+\+MODE \texorpdfstring{$\vert$}{|} I2\+C\+\_\+\+SOFTEND\+\_\+\+MODE))
\item 
\#define {\bfseries I2\+C\+\_\+\+NEXT\+\_\+\+FRAME}~((uint32\+\_\+t)(I2\+C\+\_\+\+RELOAD\+\_\+\+MODE \texorpdfstring{$\vert$}{|} I2\+C\+\_\+\+SOFTEND\+\_\+\+MODE))
\item 
\#define {\bfseries I2\+C\+\_\+\+FIRST\+\_\+\+AND\+\_\+\+LAST\+\_\+\+FRAME}~((uint32\+\_\+t)I2\+C\+\_\+\+AUTOEND\+\_\+\+MODE)
\item 
\#define {\bfseries I2\+C\+\_\+\+LAST\+\_\+\+FRAME}~((uint32\+\_\+t)I2\+C\+\_\+\+AUTOEND\+\_\+\+MODE)
\item 
\#define {\bfseries I2\+C\+\_\+\+LAST\+\_\+\+FRAME\+\_\+\+NO\+\_\+\+STOP}~((uint32\+\_\+t)I2\+C\+\_\+\+SOFTEND\+\_\+\+MODE)
\item 
\#define {\bfseries I2\+C\+\_\+\+OTHER\+\_\+\+FRAME}~(0x000000\+AAU)
\item 
\#define {\bfseries I2\+C\+\_\+\+OTHER\+\_\+\+AND\+\_\+\+LAST\+\_\+\+FRAME}~(0x0000\+AA00U)
\item 
\#define {\bfseries I2\+C\+\_\+\+ADDRESSINGMODE\+\_\+7\+BIT}~(0x00000001U)
\item 
\#define {\bfseries I2\+C\+\_\+\+ADDRESSINGMODE\+\_\+10\+BIT}~(0x00000002U)
\item 
\#define {\bfseries I2\+C\+\_\+\+DUALADDRESS\+\_\+\+DISABLE}~(0x00000000U)
\item 
\#define {\bfseries I2\+C\+\_\+\+DUALADDRESS\+\_\+\+ENABLE}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gaa6ec62ffdf8a682e5e0983add8fdfa26}{I2\+C\+\_\+\+OAR2\+\_\+\+OA2\+EN}}
\item 
\#define {\bfseries I2\+C\+\_\+\+OA2\+\_\+\+NOMASK}~((uint8\+\_\+t)0x00U)
\item 
\#define {\bfseries I2\+C\+\_\+\+OA2\+\_\+\+MASK01}~((uint8\+\_\+t)0x01U)
\item 
\#define {\bfseries I2\+C\+\_\+\+OA2\+\_\+\+MASK02}~((uint8\+\_\+t)0x02U)
\item 
\#define {\bfseries I2\+C\+\_\+\+OA2\+\_\+\+MASK03}~((uint8\+\_\+t)0x03U)
\item 
\#define {\bfseries I2\+C\+\_\+\+OA2\+\_\+\+MASK04}~((uint8\+\_\+t)0x04U)
\item 
\#define {\bfseries I2\+C\+\_\+\+OA2\+\_\+\+MASK05}~((uint8\+\_\+t)0x05U)
\item 
\#define {\bfseries I2\+C\+\_\+\+OA2\+\_\+\+MASK06}~((uint8\+\_\+t)0x06U)
\item 
\#define {\bfseries I2\+C\+\_\+\+OA2\+\_\+\+MASK07}~((uint8\+\_\+t)0x07U)
\item 
\#define {\bfseries I2\+C\+\_\+\+GENERALCALL\+\_\+\+DISABLE}~(0x00000000U)
\item 
\#define {\bfseries I2\+C\+\_\+\+GENERALCALL\+\_\+\+ENABLE}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gac28d4f433e501e727c91097dccc4616c}{I2\+C\+\_\+\+CR1\+\_\+\+GCEN}}
\item 
\#define {\bfseries I2\+C\+\_\+\+NOSTRETCH\+\_\+\+DISABLE}~(0x00000000U)
\item 
\#define {\bfseries I2\+C\+\_\+\+NOSTRETCH\+\_\+\+ENABLE}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga197aaca79f64e832af3a0a0864c2a08c}{I2\+C\+\_\+\+CR1\+\_\+\+NOSTRETCH}}
\item 
\#define {\bfseries I2\+C\+\_\+\+MEMADD\+\_\+\+SIZE\+\_\+8\+BIT}~(0x00000001U)
\item 
\#define {\bfseries I2\+C\+\_\+\+MEMADD\+\_\+\+SIZE\+\_\+16\+BIT}~(0x00000002U)
\item 
\#define {\bfseries I2\+C\+\_\+\+DIRECTION\+\_\+\+TRANSMIT}~(0x00000000U)
\item 
\#define {\bfseries I2\+C\+\_\+\+DIRECTION\+\_\+\+RECEIVE}~(0x00000001U)
\item 
\#define {\bfseries I2\+C\+\_\+\+RELOAD\+\_\+\+MODE}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga21a796045451013c964ef8b12ca6c9bb}{I2\+C\+\_\+\+CR2\+\_\+\+RELOAD}}
\item 
\#define {\bfseries I2\+C\+\_\+\+AUTOEND\+\_\+\+MODE}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gabcf789c74e217ec8967bcabc156a6c54}{I2\+C\+\_\+\+CR2\+\_\+\+AUTOEND}}
\item 
\#define {\bfseries I2\+C\+\_\+\+SOFTEND\+\_\+\+MODE}~(0x00000000U)
\item 
\#define {\bfseries I2\+C\+\_\+\+NO\+\_\+\+STARTSTOP}~(0x00000000U)
\item 
\#define {\bfseries I2\+C\+\_\+\+GENERATE\+\_\+\+STOP}~(uint32\+\_\+t)(0x80000000U \texorpdfstring{$\vert$}{|} \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga37007be453dd8a637be2d793d3b5f2a2}{I2\+C\+\_\+\+CR2\+\_\+\+STOP}})
\item 
\#define {\bfseries I2\+C\+\_\+\+GENERATE\+\_\+\+START\+\_\+\+READ}~(uint32\+\_\+t)(0x80000000U \texorpdfstring{$\vert$}{|} \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga5ac78b87a12a9eaf564f5a3f99928478}{I2\+C\+\_\+\+CR2\+\_\+\+START}} \texorpdfstring{$\vert$}{|} \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga268ec714bbe4a75ea098c0e230a87697}{I2\+C\+\_\+\+CR2\+\_\+\+RD\+\_\+\+WRN}})
\item 
\#define {\bfseries I2\+C\+\_\+\+GENERATE\+\_\+\+START\+\_\+\+WRITE}~(uint32\+\_\+t)(0x80000000U \texorpdfstring{$\vert$}{|} \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga5ac78b87a12a9eaf564f5a3f99928478}{I2\+C\+\_\+\+CR2\+\_\+\+START}})
\item 
\#define {\bfseries I2\+C\+\_\+\+IT\+\_\+\+ERRI}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga75e971012a02f9dad47a1629c6f5d956}{I2\+C\+\_\+\+CR1\+\_\+\+ERRIE}}
\item 
\#define {\bfseries I2\+C\+\_\+\+IT\+\_\+\+TCI}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga6b37e64bdf6399ef12c3df77bcb1634f}{I2\+C\+\_\+\+CR1\+\_\+\+TCIE}}
\item 
\#define {\bfseries I2\+C\+\_\+\+IT\+\_\+\+STOPI}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga1f1576cb1a2cd847f55fe2a0820bb166}{I2\+C\+\_\+\+CR1\+\_\+\+STOPIE}}
\item 
\#define {\bfseries I2\+C\+\_\+\+IT\+\_\+\+NACKI}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gae3f71f7a55e13a467b2a5ed639e0fe18}{I2\+C\+\_\+\+CR1\+\_\+\+NACKIE}}
\item 
\#define {\bfseries I2\+C\+\_\+\+IT\+\_\+\+ADDRI}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga275e85befdb3d7ea7b5eb402cec574ec}{I2\+C\+\_\+\+CR1\+\_\+\+ADDRIE}}
\item 
\#define {\bfseries I2\+C\+\_\+\+IT\+\_\+\+RXI}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gaf1fc89bf142bfc08ee78763e6e27cd80}{I2\+C\+\_\+\+CR1\+\_\+\+RXIE}}
\item 
\#define {\bfseries I2\+C\+\_\+\+IT\+\_\+\+TXI}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga8bd36da8f72bc91040e63af07dd6b5a4}{I2\+C\+\_\+\+CR1\+\_\+\+TXIE}}
\item 
\#define {\bfseries I2\+C\+\_\+\+FLAG\+\_\+\+TXE}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga1dfec198395c0f88454a86bacff60351}{I2\+C\+\_\+\+ISR\+\_\+\+TXE}}
\item 
\#define {\bfseries I2\+C\+\_\+\+FLAG\+\_\+\+TXIS}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gaa848ab3d120a27401203329941c9dcb5}{I2\+C\+\_\+\+ISR\+\_\+\+TXIS}}
\item 
\#define {\bfseries I2\+C\+\_\+\+FLAG\+\_\+\+RXNE}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga0afd4e99e26dcec57a0f3be4dae2c022}{I2\+C\+\_\+\+ISR\+\_\+\+RXNE}}
\item 
\#define {\bfseries I2\+C\+\_\+\+FLAG\+\_\+\+ADDR}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga0c1a844fb3e55ca9db318d0bc2db4a07}{I2\+C\+\_\+\+ISR\+\_\+\+ADDR}}
\item 
\#define {\bfseries I2\+C\+\_\+\+FLAG\+\_\+\+AF}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gad2fb99c13292fc510cfe85bf45ac6b77}{I2\+C\+\_\+\+ISR\+\_\+\+NACKF}}
\item 
\#define {\bfseries I2\+C\+\_\+\+FLAG\+\_\+\+STOPF}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga24dee623aba3059485449f8ce7d061b7}{I2\+C\+\_\+\+ISR\+\_\+\+STOPF}}
\item 
\#define {\bfseries I2\+C\+\_\+\+FLAG\+\_\+\+TC}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gac47bed557caa744aa763e1a8d0eba04d}{I2\+C\+\_\+\+ISR\+\_\+\+TC}}
\item 
\#define {\bfseries I2\+C\+\_\+\+FLAG\+\_\+\+TCR}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga76008be670a9a4829aaf3753c79b3bbd}{I2\+C\+\_\+\+ISR\+\_\+\+TCR}}
\item 
\#define {\bfseries I2\+C\+\_\+\+FLAG\+\_\+\+BERR}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga0dd0d8fdc41303a1c31fc7466301be07}{I2\+C\+\_\+\+ISR\+\_\+\+BERR}}
\item 
\#define {\bfseries I2\+C\+\_\+\+FLAG\+\_\+\+ARLO}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga54ae33fec99aa351621ba6b483fbead3}{I2\+C\+\_\+\+ISR\+\_\+\+ARLO}}
\item 
\#define {\bfseries I2\+C\+\_\+\+FLAG\+\_\+\+OVR}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gaf5976110d93d2f36f50c4c6467510914}{I2\+C\+\_\+\+ISR\+\_\+\+OVR}}
\item 
\#define {\bfseries I2\+C\+\_\+\+FLAG\+\_\+\+PECERR}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga8b1d42968194fb42f9cc9bb2c2806281}{I2\+C\+\_\+\+ISR\+\_\+\+PECERR}}
\item 
\#define {\bfseries I2\+C\+\_\+\+FLAG\+\_\+\+TIMEOUT}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga63fc8ce165c42d0d719c45e58a82f574}{I2\+C\+\_\+\+ISR\+\_\+\+TIMEOUT}}
\item 
\#define {\bfseries I2\+C\+\_\+\+FLAG\+\_\+\+ALERT}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga4c6c779bca999450c595fc797a1fdeec}{I2\+C\+\_\+\+ISR\+\_\+\+ALERT}}
\item 
\#define {\bfseries I2\+C\+\_\+\+FLAG\+\_\+\+BUSY}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga12ba21dc10ca08a2063a1c4672ffb886}{I2\+C\+\_\+\+ISR\+\_\+\+BUSY}}
\item 
\#define {\bfseries I2\+C\+\_\+\+FLAG\+\_\+\+DIR}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gaa4890d7deb94106f946b28a7309e22aa}{I2\+C\+\_\+\+ISR\+\_\+\+DIR}}
\item 
\#define \mbox{\hyperlink{group___i2_c___exported___macros_ga74c8fd72a78882720c28448ce8bd33d8}{\+\_\+\+\_\+\+HAL\+\_\+\+I2\+C\+\_\+\+RESET\+\_\+\+HANDLE\+\_\+\+STATE}}(\+\_\+\+\_\+\+HANDLE\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Reset I2C handle state. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___i2_c___exported___macros_gac9d8b249b06b2d30f987acc9ceebd1d9}{\+\_\+\+\_\+\+HAL\+\_\+\+I2\+C\+\_\+\+ENABLE\+\_\+\+IT}}(\+\_\+\+\_\+\+HANDLE\+\_\+\+\_\+,  \+\_\+\+\_\+\+INTERRUPT\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Enable the specified I2C interrupt. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___i2_c___exported___macros_ga33d0c7202ae298fa3ae128c5da49d455}{\+\_\+\+\_\+\+HAL\+\_\+\+I2\+C\+\_\+\+DISABLE\+\_\+\+IT}}(\+\_\+\+\_\+\+HANDLE\+\_\+\+\_\+,  \+\_\+\+\_\+\+INTERRUPT\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Disable the specified I2C interrupt. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___i2_c___exported___macros_ga932024bf4a259e0cdaf9e50b38e3d41a}{\+\_\+\+\_\+\+HAL\+\_\+\+I2\+C\+\_\+\+GET\+\_\+\+IT\+\_\+\+SOURCE}}(\+\_\+\+\_\+\+HANDLE\+\_\+\+\_\+,  \+\_\+\+\_\+\+INTERRUPT\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Check whether the specified I2C interrupt source is enabled or not. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___i2_c___exported___macros_gafbc0a6e4113be03100fbae1314a8b395}{I2\+C\+\_\+\+FLAG\+\_\+\+MASK}}~(0x0001\+FFFFU)
\begin{DoxyCompactList}\small\item\em Check whether the specified I2C flag is set or not. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___i2_c___exported___macros_gafbdf01a7dc3183de7af56456cab93551}{\+\_\+\+\_\+\+HAL\+\_\+\+I2\+C\+\_\+\+GET\+\_\+\+FLAG}}(\+\_\+\+\_\+\+HANDLE\+\_\+\+\_\+,  \+\_\+\+\_\+\+FLAG\+\_\+\+\_\+)
\item 
\#define \mbox{\hyperlink{group___i2_c___exported___macros_ga933e2ea67e86db857a06b70a93be1186}{\+\_\+\+\_\+\+HAL\+\_\+\+I2\+C\+\_\+\+CLEAR\+\_\+\+FLAG}}(\+\_\+\+\_\+\+HANDLE\+\_\+\+\_\+,  \+\_\+\+\_\+\+FLAG\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Clear the I2C pending flags which are cleared by writing 1 in a specific bit. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___i2_c___exported___macros_gacff412c47b0c1d63ef3b2a07f65988b7}{\+\_\+\+\_\+\+HAL\+\_\+\+I2\+C\+\_\+\+ENABLE}}(\+\_\+\+\_\+\+HANDLE\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Enable the specified I2C peripheral. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___i2_c___exported___macros_ga3d6a35da02ca72537a15570912c80412}{\+\_\+\+\_\+\+HAL\+\_\+\+I2\+C\+\_\+\+DISABLE}}(\+\_\+\+\_\+\+HANDLE\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Disable the specified I2C peripheral. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___i2_c___exported___macros_ga11f1b2e130ffa7e62d82ff1ebdb3f4f4}{\+\_\+\+\_\+\+HAL\+\_\+\+I2\+C\+\_\+\+GENERATE\+\_\+\+NACK}}(\+\_\+\+\_\+\+HANDLE\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Generate a Non-\/\+Acknowledge I2C peripheral in Slave mode. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___i2_c___private___macro_ga14b20c50be9fcafef1ce2f0b962b39a9}{IS\+\_\+\+I2\+C\+\_\+\+ADDRESSING\+\_\+\+MODE}}(MODE)
\item 
\#define \mbox{\hyperlink{group___i2_c___private___macro_gae683c113d4088dfae90fbe6677f8296a}{IS\+\_\+\+I2\+C\+\_\+\+DUAL\+\_\+\+ADDRESS}}(ADDRESS)
\item 
\#define \mbox{\hyperlink{group___i2_c___private___macro_ga4f5ba081bbab937fa5137340492def13}{IS\+\_\+\+I2\+C\+\_\+\+OWN\+\_\+\+ADDRESS2\+\_\+\+MASK}}(MASK)
\item 
\#define \mbox{\hyperlink{group___i2_c___private___macro_ga36a9a7855d7f35a6b03b05c6079bf149}{IS\+\_\+\+I2\+C\+\_\+\+GENERAL\+\_\+\+CALL}}(CALL)
\item 
\#define \mbox{\hyperlink{group___i2_c___private___macro_gaf7d844f7c7f5c96067468ab47971d0fd}{IS\+\_\+\+I2\+C\+\_\+\+NO\+\_\+\+STRETCH}}(STRETCH)
\item 
\#define \mbox{\hyperlink{group___i2_c___private___macro_gace95d2b6add7feef5805f1fa6d2e46be}{IS\+\_\+\+I2\+C\+\_\+\+MEMADD\+\_\+\+SIZE}}(SIZE)
\item 
\#define \mbox{\hyperlink{group___i2_c___private___macro_gafaa6130d7e7e11240349d9e1476c7f06}{IS\+\_\+\+TRANSFER\+\_\+\+MODE}}(MODE)
\item 
\#define \mbox{\hyperlink{group___i2_c___private___macro_ga035522b30af949e6643a5c34bd07f9d2}{IS\+\_\+\+TRANSFER\+\_\+\+REQUEST}}(REQUEST)
\item 
\#define \mbox{\hyperlink{group___i2_c___private___macro_ga8f3522af9ffef268641698ac80f77859}{IS\+\_\+\+I2\+C\+\_\+\+TRANSFER\+\_\+\+OPTIONS\+\_\+\+REQUEST}}(REQUEST)
\item 
\#define \mbox{\hyperlink{group___i2_c___private___macro_ga13a3986011ca018dd12ff39ea3bec11b}{IS\+\_\+\+I2\+C\+\_\+\+TRANSFER\+\_\+\+OTHER\+\_\+\+OPTIONS\+\_\+\+REQUEST}}(REQUEST)
\item 
\#define \mbox{\hyperlink{group___i2_c___private___macro_ga84085a3fd5b43f29ec449d86560a9378}{I2\+C\+\_\+\+RESET\+\_\+\+CR2}}(\+\_\+\+\_\+\+HANDLE\+\_\+\+\_\+)
\item 
\#define \mbox{\hyperlink{group___i2_c___private___macro_ga30d76b55c39e04efb077f47eb454261d}{I2\+C\+\_\+\+GET\+\_\+\+ADDR\+\_\+\+MATCH}}(\+\_\+\+\_\+\+HANDLE\+\_\+\+\_\+)
\item 
\#define \mbox{\hyperlink{group___i2_c___private___macro_ga0359d435a6d984b3fefdc2da709e5764}{I2\+C\+\_\+\+GET\+\_\+\+DIR}}(\+\_\+\+\_\+\+HANDLE\+\_\+\+\_\+)
\item 
\#define \mbox{\hyperlink{group___i2_c___private___macro_ga1bc559a860da12ee5a7517548facbc57}{I2\+C\+\_\+\+GET\+\_\+\+STOP\+\_\+\+MODE}}(\+\_\+\+\_\+\+HANDLE\+\_\+\+\_\+)
\item 
\#define \mbox{\hyperlink{group___i2_c___private___macro_gaa80106d084f4027f8f341f2c3c49dcfa}{I2\+C\+\_\+\+GET\+\_\+\+OWN\+\_\+\+ADDRESS1}}(\+\_\+\+\_\+\+HANDLE\+\_\+\+\_\+)
\item 
\#define \mbox{\hyperlink{group___i2_c___private___macro_gad0b113e974debf6a9af783e1fe08ef23}{I2\+C\+\_\+\+GET\+\_\+\+OWN\+\_\+\+ADDRESS2}}(\+\_\+\+\_\+\+HANDLE\+\_\+\+\_\+)
\item 
\#define \mbox{\hyperlink{group___i2_c___private___macro_gad84e8b9523d45b6105b4d5cb68994a79}{IS\+\_\+\+I2\+C\+\_\+\+OWN\+\_\+\+ADDRESS1}}(ADDRESS1)
\item 
\#define \mbox{\hyperlink{group___i2_c___private___macro_ga83001d53612b83ee90730d3bb2732537}{IS\+\_\+\+I2\+C\+\_\+\+OWN\+\_\+\+ADDRESS2}}(ADDRESS2)
\item 
\#define \mbox{\hyperlink{group___i2_c___private___macro_ga2e42fa55be22240dc5a54a0304d01cfb}{I2\+C\+\_\+\+MEM\+\_\+\+ADD\+\_\+\+MSB}}(\+\_\+\+\_\+\+ADDRESS\+\_\+\+\_\+)
\item 
\#define \mbox{\hyperlink{group___i2_c___private___macro_ga9c8f1a763307d0c37bb4e2dcfdf3bb9f}{I2\+C\+\_\+\+MEM\+\_\+\+ADD\+\_\+\+LSB}}(\+\_\+\+\_\+\+ADDRESS\+\_\+\+\_\+)
\item 
\#define \mbox{\hyperlink{group___i2_c___private___macro_ga5212d1dbe376d10b7ec3060032283a33}{I2\+C\+\_\+\+GENERATE\+\_\+\+START}}(\+\_\+\+\_\+\+ADDMODE\+\_\+\+\_\+,  \+\_\+\+\_\+\+ADDRESS\+\_\+\+\_\+)
\item 
\#define \mbox{\hyperlink{group___i2_c___private___macro_ga31873e0595e29c80cffe00c2d2e073ab}{I2\+C\+\_\+\+CHECK\+\_\+\+FLAG}}(\+\_\+\+\_\+\+ISR\+\_\+\+\_\+,  \+\_\+\+\_\+\+FLAG\+\_\+\+\_\+)
\item 
\#define \mbox{\hyperlink{group___i2_c___private___macro_gacc7c83a67d99d759923c6907f1a1751f}{I2\+C\+\_\+\+CHECK\+\_\+\+IT\+\_\+\+SOURCE}}(\+\_\+\+\_\+\+CR1\+\_\+\+\_\+,  \+\_\+\+\_\+\+IT\+\_\+\+\_\+)
\end{DoxyCompactItemize}
\doxysubsubsection*{Typedefs}
\begin{DoxyCompactItemize}
\item 
typedef struct \mbox{\hyperlink{struct_____i2_c___handle_type_def}{\+\_\+\+\_\+\+I2\+C\+\_\+\+Handle\+Type\+Def}} {\bfseries I2\+C\+\_\+\+Handle\+Type\+Def}
\end{DoxyCompactItemize}
\doxysubsubsection*{Enumerations}
\begin{DoxyCompactItemize}
\item 
enum \mbox{\hyperlink{group___h_a_l__state__structure__definition_gaef355af8eab251ae2a19ee164ad81c37}{HAL\+\_\+\+I2\+C\+\_\+\+State\+Type\+Def}} \{ \newline
\mbox{\hyperlink{group___h_a_l__state__structure__definition_ggaef355af8eab251ae2a19ee164ad81c37a91ba08634e08d7287940f1bc5a37eeff}{HAL\+\_\+\+I2\+C\+\_\+\+STATE\+\_\+\+RESET}} = 0x00U
, \mbox{\hyperlink{group___h_a_l__state__structure__definition_ggaef355af8eab251ae2a19ee164ad81c37af859ce60c5e462b0bfde3a5010bc72d1}{HAL\+\_\+\+I2\+C\+\_\+\+STATE\+\_\+\+READY}} = 0x20U
, \mbox{\hyperlink{group___h_a_l__state__structure__definition_ggaef355af8eab251ae2a19ee164ad81c37a0c503d6c0388f0d872b368557e278b5a}{HAL\+\_\+\+I2\+C\+\_\+\+STATE\+\_\+\+BUSY}} = 0x24U
, \mbox{\hyperlink{group___h_a_l__state__structure__definition_ggaef355af8eab251ae2a19ee164ad81c37acb3a9e3d4d1076e0f4e65f91ca0161bc}{HAL\+\_\+\+I2\+C\+\_\+\+STATE\+\_\+\+BUSY\+\_\+\+TX}} = 0x21U
, \newline
\mbox{\hyperlink{group___h_a_l__state__structure__definition_ggaef355af8eab251ae2a19ee164ad81c37a4ea4ecc2dc3cb64c4877c123d9d73170}{HAL\+\_\+\+I2\+C\+\_\+\+STATE\+\_\+\+BUSY\+\_\+\+RX}} = 0x22U
, \mbox{\hyperlink{group___h_a_l__state__structure__definition_ggaef355af8eab251ae2a19ee164ad81c37a13518f06f54c7515100e86bb8d6e0779}{HAL\+\_\+\+I2\+C\+\_\+\+STATE\+\_\+\+LISTEN}} = 0x28U
, \mbox{\hyperlink{group___h_a_l__state__structure__definition_ggaef355af8eab251ae2a19ee164ad81c37a14d22553a60819b276582e08459f30b0}{HAL\+\_\+\+I2\+C\+\_\+\+STATE\+\_\+\+BUSY\+\_\+\+TX\+\_\+\+LISTEN}} = 0x29U
, \mbox{\hyperlink{group___h_a_l__state__structure__definition_ggaef355af8eab251ae2a19ee164ad81c37a8aec2547eedf1c9924f8efed33e3b5c5}{HAL\+\_\+\+I2\+C\+\_\+\+STATE\+\_\+\+BUSY\+\_\+\+RX\+\_\+\+LISTEN}} = 0x2\+AU
, \newline
\mbox{\hyperlink{group___h_a_l__state__structure__definition_ggaef355af8eab251ae2a19ee164ad81c37a2c6f6d1fef0847f9da51153b5c295249}{HAL\+\_\+\+I2\+C\+\_\+\+STATE\+\_\+\+ABORT}} = 0x60U
 \}
\item 
enum \mbox{\hyperlink{group___h_a_l__mode__structure__definition_gabcbb7b844f2ffd63c4e530c117882062}{HAL\+\_\+\+I2\+C\+\_\+\+Mode\+Type\+Def}} \{ \mbox{\hyperlink{group___h_a_l__mode__structure__definition_ggabcbb7b844f2ffd63c4e530c117882062a98c8fd642b7ac45a23479bd597fc7a71}{HAL\+\_\+\+I2\+C\+\_\+\+MODE\+\_\+\+NONE}} = 0x00U
, \mbox{\hyperlink{group___h_a_l__mode__structure__definition_ggabcbb7b844f2ffd63c4e530c117882062a1eea98660a170dd7b191c9dfe46da6d2}{HAL\+\_\+\+I2\+C\+\_\+\+MODE\+\_\+\+MASTER}} = 0x10U
, \mbox{\hyperlink{group___h_a_l__mode__structure__definition_ggabcbb7b844f2ffd63c4e530c117882062a817358d19d278261f2047a5ec8ec6b53}{HAL\+\_\+\+I2\+C\+\_\+\+MODE\+\_\+\+SLAVE}} = 0x20U
, \mbox{\hyperlink{group___h_a_l__mode__structure__definition_ggabcbb7b844f2ffd63c4e530c117882062a3f592bd942f973242aac6b7df79f3f1e}{HAL\+\_\+\+I2\+C\+\_\+\+MODE\+\_\+\+MEM}} = 0x40U
 \}
\end{DoxyCompactItemize}
\doxysubsubsection*{Functions}
\begin{DoxyCompactItemize}
\item 
\mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\+\_\+\+Status\+Type\+Def}} {\bfseries HAL\+\_\+\+I2\+C\+\_\+\+Init} (\mbox{\hyperlink{struct_____i2_c___handle_type_def}{I2\+C\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}hi2c)
\item 
\mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\+\_\+\+Status\+Type\+Def}} {\bfseries HAL\+\_\+\+I2\+C\+\_\+\+De\+Init} (\mbox{\hyperlink{struct_____i2_c___handle_type_def}{I2\+C\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}hi2c)
\item 
void {\bfseries HAL\+\_\+\+I2\+C\+\_\+\+Msp\+Init} (\mbox{\hyperlink{struct_____i2_c___handle_type_def}{I2\+C\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}hi2c)
\item 
void {\bfseries HAL\+\_\+\+I2\+C\+\_\+\+Msp\+De\+Init} (\mbox{\hyperlink{struct_____i2_c___handle_type_def}{I2\+C\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}hi2c)
\item 
\mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\+\_\+\+Status\+Type\+Def}} {\bfseries HAL\+\_\+\+I2\+C\+\_\+\+Master\+\_\+\+Transmit} (\mbox{\hyperlink{struct_____i2_c___handle_type_def}{I2\+C\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}hi2c, uint16\+\_\+t Dev\+Address, uint8\+\_\+t \texorpdfstring{$\ast$}{*}p\+Data, uint16\+\_\+t Size, uint32\+\_\+t Timeout)
\item 
\mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\+\_\+\+Status\+Type\+Def}} {\bfseries HAL\+\_\+\+I2\+C\+\_\+\+Master\+\_\+\+Receive} (\mbox{\hyperlink{struct_____i2_c___handle_type_def}{I2\+C\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}hi2c, uint16\+\_\+t Dev\+Address, uint8\+\_\+t \texorpdfstring{$\ast$}{*}p\+Data, uint16\+\_\+t Size, uint32\+\_\+t Timeout)
\item 
\mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\+\_\+\+Status\+Type\+Def}} {\bfseries HAL\+\_\+\+I2\+C\+\_\+\+Slave\+\_\+\+Transmit} (\mbox{\hyperlink{struct_____i2_c___handle_type_def}{I2\+C\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}hi2c, uint8\+\_\+t \texorpdfstring{$\ast$}{*}p\+Data, uint16\+\_\+t Size, uint32\+\_\+t Timeout)
\item 
\mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\+\_\+\+Status\+Type\+Def}} {\bfseries HAL\+\_\+\+I2\+C\+\_\+\+Slave\+\_\+\+Receive} (\mbox{\hyperlink{struct_____i2_c___handle_type_def}{I2\+C\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}hi2c, uint8\+\_\+t \texorpdfstring{$\ast$}{*}p\+Data, uint16\+\_\+t Size, uint32\+\_\+t Timeout)
\item 
\mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\+\_\+\+Status\+Type\+Def}} {\bfseries HAL\+\_\+\+I2\+C\+\_\+\+Mem\+\_\+\+Write} (\mbox{\hyperlink{struct_____i2_c___handle_type_def}{I2\+C\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}hi2c, uint16\+\_\+t Dev\+Address, uint16\+\_\+t Mem\+Address, uint16\+\_\+t Mem\+Add\+Size, uint8\+\_\+t \texorpdfstring{$\ast$}{*}p\+Data, uint16\+\_\+t Size, uint32\+\_\+t Timeout)
\item 
\mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\+\_\+\+Status\+Type\+Def}} {\bfseries HAL\+\_\+\+I2\+C\+\_\+\+Mem\+\_\+\+Read} (\mbox{\hyperlink{struct_____i2_c___handle_type_def}{I2\+C\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}hi2c, uint16\+\_\+t Dev\+Address, uint16\+\_\+t Mem\+Address, uint16\+\_\+t Mem\+Add\+Size, uint8\+\_\+t \texorpdfstring{$\ast$}{*}p\+Data, uint16\+\_\+t Size, uint32\+\_\+t Timeout)
\item 
\mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\+\_\+\+Status\+Type\+Def}} {\bfseries HAL\+\_\+\+I2\+C\+\_\+\+Is\+Device\+Ready} (\mbox{\hyperlink{struct_____i2_c___handle_type_def}{I2\+C\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}hi2c, uint16\+\_\+t Dev\+Address, uint32\+\_\+t Trials, uint32\+\_\+t Timeout)
\item 
\mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\+\_\+\+Status\+Type\+Def}} {\bfseries HAL\+\_\+\+I2\+C\+\_\+\+Master\+\_\+\+Transmit\+\_\+\+IT} (\mbox{\hyperlink{struct_____i2_c___handle_type_def}{I2\+C\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}hi2c, uint16\+\_\+t Dev\+Address, uint8\+\_\+t \texorpdfstring{$\ast$}{*}p\+Data, uint16\+\_\+t Size)
\item 
\mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\+\_\+\+Status\+Type\+Def}} {\bfseries HAL\+\_\+\+I2\+C\+\_\+\+Master\+\_\+\+Receive\+\_\+\+IT} (\mbox{\hyperlink{struct_____i2_c___handle_type_def}{I2\+C\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}hi2c, uint16\+\_\+t Dev\+Address, uint8\+\_\+t \texorpdfstring{$\ast$}{*}p\+Data, uint16\+\_\+t Size)
\item 
\mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\+\_\+\+Status\+Type\+Def}} {\bfseries HAL\+\_\+\+I2\+C\+\_\+\+Slave\+\_\+\+Transmit\+\_\+\+IT} (\mbox{\hyperlink{struct_____i2_c___handle_type_def}{I2\+C\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}hi2c, uint8\+\_\+t \texorpdfstring{$\ast$}{*}p\+Data, uint16\+\_\+t Size)
\item 
\mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\+\_\+\+Status\+Type\+Def}} {\bfseries HAL\+\_\+\+I2\+C\+\_\+\+Slave\+\_\+\+Receive\+\_\+\+IT} (\mbox{\hyperlink{struct_____i2_c___handle_type_def}{I2\+C\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}hi2c, uint8\+\_\+t \texorpdfstring{$\ast$}{*}p\+Data, uint16\+\_\+t Size)
\item 
\mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\+\_\+\+Status\+Type\+Def}} {\bfseries HAL\+\_\+\+I2\+C\+\_\+\+Mem\+\_\+\+Write\+\_\+\+IT} (\mbox{\hyperlink{struct_____i2_c___handle_type_def}{I2\+C\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}hi2c, uint16\+\_\+t Dev\+Address, uint16\+\_\+t Mem\+Address, uint16\+\_\+t Mem\+Add\+Size, uint8\+\_\+t \texorpdfstring{$\ast$}{*}p\+Data, uint16\+\_\+t Size)
\item 
\mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\+\_\+\+Status\+Type\+Def}} {\bfseries HAL\+\_\+\+I2\+C\+\_\+\+Mem\+\_\+\+Read\+\_\+\+IT} (\mbox{\hyperlink{struct_____i2_c___handle_type_def}{I2\+C\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}hi2c, uint16\+\_\+t Dev\+Address, uint16\+\_\+t Mem\+Address, uint16\+\_\+t Mem\+Add\+Size, uint8\+\_\+t \texorpdfstring{$\ast$}{*}p\+Data, uint16\+\_\+t Size)
\item 
\mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\+\_\+\+Status\+Type\+Def}} {\bfseries HAL\+\_\+\+I2\+C\+\_\+\+Master\+\_\+\+Seq\+\_\+\+Transmit\+\_\+\+IT} (\mbox{\hyperlink{struct_____i2_c___handle_type_def}{I2\+C\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}hi2c, uint16\+\_\+t Dev\+Address, uint8\+\_\+t \texorpdfstring{$\ast$}{*}p\+Data, uint16\+\_\+t Size, uint32\+\_\+t Xfer\+Options)
\item 
\mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\+\_\+\+Status\+Type\+Def}} {\bfseries HAL\+\_\+\+I2\+C\+\_\+\+Master\+\_\+\+Seq\+\_\+\+Receive\+\_\+\+IT} (\mbox{\hyperlink{struct_____i2_c___handle_type_def}{I2\+C\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}hi2c, uint16\+\_\+t Dev\+Address, uint8\+\_\+t \texorpdfstring{$\ast$}{*}p\+Data, uint16\+\_\+t Size, uint32\+\_\+t Xfer\+Options)
\item 
\mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\+\_\+\+Status\+Type\+Def}} {\bfseries HAL\+\_\+\+I2\+C\+\_\+\+Slave\+\_\+\+Seq\+\_\+\+Transmit\+\_\+\+IT} (\mbox{\hyperlink{struct_____i2_c___handle_type_def}{I2\+C\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}hi2c, uint8\+\_\+t \texorpdfstring{$\ast$}{*}p\+Data, uint16\+\_\+t Size, uint32\+\_\+t Xfer\+Options)
\item 
\mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\+\_\+\+Status\+Type\+Def}} {\bfseries HAL\+\_\+\+I2\+C\+\_\+\+Slave\+\_\+\+Seq\+\_\+\+Receive\+\_\+\+IT} (\mbox{\hyperlink{struct_____i2_c___handle_type_def}{I2\+C\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}hi2c, uint8\+\_\+t \texorpdfstring{$\ast$}{*}p\+Data, uint16\+\_\+t Size, uint32\+\_\+t Xfer\+Options)
\item 
\mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\+\_\+\+Status\+Type\+Def}} {\bfseries HAL\+\_\+\+I2\+C\+\_\+\+Enable\+Listen\+\_\+\+IT} (\mbox{\hyperlink{struct_____i2_c___handle_type_def}{I2\+C\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}hi2c)
\item 
\mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\+\_\+\+Status\+Type\+Def}} {\bfseries HAL\+\_\+\+I2\+C\+\_\+\+Disable\+Listen\+\_\+\+IT} (\mbox{\hyperlink{struct_____i2_c___handle_type_def}{I2\+C\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}hi2c)
\item 
\mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\+\_\+\+Status\+Type\+Def}} {\bfseries HAL\+\_\+\+I2\+C\+\_\+\+Master\+\_\+\+Abort\+\_\+\+IT} (\mbox{\hyperlink{struct_____i2_c___handle_type_def}{I2\+C\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}hi2c, uint16\+\_\+t Dev\+Address)
\item 
\mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\+\_\+\+Status\+Type\+Def}} {\bfseries HAL\+\_\+\+I2\+C\+\_\+\+Master\+\_\+\+Transmit\+\_\+\+DMA} (\mbox{\hyperlink{struct_____i2_c___handle_type_def}{I2\+C\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}hi2c, uint16\+\_\+t Dev\+Address, uint8\+\_\+t \texorpdfstring{$\ast$}{*}p\+Data, uint16\+\_\+t Size)
\item 
\mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\+\_\+\+Status\+Type\+Def}} {\bfseries HAL\+\_\+\+I2\+C\+\_\+\+Master\+\_\+\+Receive\+\_\+\+DMA} (\mbox{\hyperlink{struct_____i2_c___handle_type_def}{I2\+C\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}hi2c, uint16\+\_\+t Dev\+Address, uint8\+\_\+t \texorpdfstring{$\ast$}{*}p\+Data, uint16\+\_\+t Size)
\item 
\mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\+\_\+\+Status\+Type\+Def}} {\bfseries HAL\+\_\+\+I2\+C\+\_\+\+Slave\+\_\+\+Transmit\+\_\+\+DMA} (\mbox{\hyperlink{struct_____i2_c___handle_type_def}{I2\+C\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}hi2c, uint8\+\_\+t \texorpdfstring{$\ast$}{*}p\+Data, uint16\+\_\+t Size)
\item 
\mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\+\_\+\+Status\+Type\+Def}} {\bfseries HAL\+\_\+\+I2\+C\+\_\+\+Slave\+\_\+\+Receive\+\_\+\+DMA} (\mbox{\hyperlink{struct_____i2_c___handle_type_def}{I2\+C\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}hi2c, uint8\+\_\+t \texorpdfstring{$\ast$}{*}p\+Data, uint16\+\_\+t Size)
\item 
\mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\+\_\+\+Status\+Type\+Def}} {\bfseries HAL\+\_\+\+I2\+C\+\_\+\+Mem\+\_\+\+Write\+\_\+\+DMA} (\mbox{\hyperlink{struct_____i2_c___handle_type_def}{I2\+C\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}hi2c, uint16\+\_\+t Dev\+Address, uint16\+\_\+t Mem\+Address, uint16\+\_\+t Mem\+Add\+Size, uint8\+\_\+t \texorpdfstring{$\ast$}{*}p\+Data, uint16\+\_\+t Size)
\item 
\mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\+\_\+\+Status\+Type\+Def}} {\bfseries HAL\+\_\+\+I2\+C\+\_\+\+Mem\+\_\+\+Read\+\_\+\+DMA} (\mbox{\hyperlink{struct_____i2_c___handle_type_def}{I2\+C\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}hi2c, uint16\+\_\+t Dev\+Address, uint16\+\_\+t Mem\+Address, uint16\+\_\+t Mem\+Add\+Size, uint8\+\_\+t \texorpdfstring{$\ast$}{*}p\+Data, uint16\+\_\+t Size)
\item 
\mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\+\_\+\+Status\+Type\+Def}} {\bfseries HAL\+\_\+\+I2\+C\+\_\+\+Master\+\_\+\+Seq\+\_\+\+Transmit\+\_\+\+DMA} (\mbox{\hyperlink{struct_____i2_c___handle_type_def}{I2\+C\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}hi2c, uint16\+\_\+t Dev\+Address, uint8\+\_\+t \texorpdfstring{$\ast$}{*}p\+Data, uint16\+\_\+t Size, uint32\+\_\+t Xfer\+Options)
\item 
\mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\+\_\+\+Status\+Type\+Def}} {\bfseries HAL\+\_\+\+I2\+C\+\_\+\+Master\+\_\+\+Seq\+\_\+\+Receive\+\_\+\+DMA} (\mbox{\hyperlink{struct_____i2_c___handle_type_def}{I2\+C\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}hi2c, uint16\+\_\+t Dev\+Address, uint8\+\_\+t \texorpdfstring{$\ast$}{*}p\+Data, uint16\+\_\+t Size, uint32\+\_\+t Xfer\+Options)
\item 
\mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\+\_\+\+Status\+Type\+Def}} {\bfseries HAL\+\_\+\+I2\+C\+\_\+\+Slave\+\_\+\+Seq\+\_\+\+Transmit\+\_\+\+DMA} (\mbox{\hyperlink{struct_____i2_c___handle_type_def}{I2\+C\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}hi2c, uint8\+\_\+t \texorpdfstring{$\ast$}{*}p\+Data, uint16\+\_\+t Size, uint32\+\_\+t Xfer\+Options)
\item 
\mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\+\_\+\+Status\+Type\+Def}} {\bfseries HAL\+\_\+\+I2\+C\+\_\+\+Slave\+\_\+\+Seq\+\_\+\+Receive\+\_\+\+DMA} (\mbox{\hyperlink{struct_____i2_c___handle_type_def}{I2\+C\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}hi2c, uint8\+\_\+t \texorpdfstring{$\ast$}{*}p\+Data, uint16\+\_\+t Size, uint32\+\_\+t Xfer\+Options)
\item 
void {\bfseries HAL\+\_\+\+I2\+C\+\_\+\+EV\+\_\+\+IRQHandler} (\mbox{\hyperlink{struct_____i2_c___handle_type_def}{I2\+C\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}hi2c)
\item 
void {\bfseries HAL\+\_\+\+I2\+C\+\_\+\+ER\+\_\+\+IRQHandler} (\mbox{\hyperlink{struct_____i2_c___handle_type_def}{I2\+C\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}hi2c)
\item 
void {\bfseries HAL\+\_\+\+I2\+C\+\_\+\+Master\+Tx\+Cplt\+Callback} (\mbox{\hyperlink{struct_____i2_c___handle_type_def}{I2\+C\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}hi2c)
\item 
void \mbox{\hyperlink{group___i2_c___i_r_q___handler__and___callbacks_ga5782358f977ddf450b203fc075833a1d}{HAL\+\_\+\+I2\+C\+\_\+\+Master\+Rx\+Cplt\+Callback}} (\mbox{\hyperlink{struct_____i2_c___handle_type_def}{I2\+C\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}hi2c)
\begin{DoxyCompactList}\small\item\em IIC接收完成回调函数 \end{DoxyCompactList}\item 
void {\bfseries HAL\+\_\+\+I2\+C\+\_\+\+Slave\+Tx\+Cplt\+Callback} (\mbox{\hyperlink{struct_____i2_c___handle_type_def}{I2\+C\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}hi2c)
\item 
void {\bfseries HAL\+\_\+\+I2\+C\+\_\+\+Slave\+Rx\+Cplt\+Callback} (\mbox{\hyperlink{struct_____i2_c___handle_type_def}{I2\+C\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}hi2c)
\item 
void {\bfseries HAL\+\_\+\+I2\+C\+\_\+\+Addr\+Callback} (\mbox{\hyperlink{struct_____i2_c___handle_type_def}{I2\+C\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}hi2c, uint8\+\_\+t Transfer\+Direction, uint16\+\_\+t Addr\+Match\+Code)
\item 
void {\bfseries HAL\+\_\+\+I2\+C\+\_\+\+Listen\+Cplt\+Callback} (\mbox{\hyperlink{struct_____i2_c___handle_type_def}{I2\+C\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}hi2c)
\item 
void {\bfseries HAL\+\_\+\+I2\+C\+\_\+\+Mem\+Tx\+Cplt\+Callback} (\mbox{\hyperlink{struct_____i2_c___handle_type_def}{I2\+C\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}hi2c)
\item 
void \mbox{\hyperlink{group___i2_c___i_r_q___handler__and___callbacks_gac16a95413b35f05c5ce725fefd8531a5}{HAL\+\_\+\+I2\+C\+\_\+\+Mem\+Rx\+Cplt\+Callback}} (\mbox{\hyperlink{struct_____i2_c___handle_type_def}{I2\+C\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}hi2c)
\begin{DoxyCompactList}\small\item\em 内存访问回调函数,仅做形式上的封装,仍然使用\+HAL\+\_\+\+I2\+C\+\_\+\+Master\+Rx\+Cplt\+Callback \end{DoxyCompactList}\item 
void {\bfseries HAL\+\_\+\+I2\+C\+\_\+\+Error\+Callback} (\mbox{\hyperlink{struct_____i2_c___handle_type_def}{I2\+C\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}hi2c)
\item 
void {\bfseries HAL\+\_\+\+I2\+C\+\_\+\+Abort\+Cplt\+Callback} (\mbox{\hyperlink{struct_____i2_c___handle_type_def}{I2\+C\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}hi2c)
\item 
\mbox{\hyperlink{group___h_a_l__state__structure__definition_gaef355af8eab251ae2a19ee164ad81c37}{HAL\+\_\+\+I2\+C\+\_\+\+State\+Type\+Def}} {\bfseries HAL\+\_\+\+I2\+C\+\_\+\+Get\+State} (const \mbox{\hyperlink{struct_____i2_c___handle_type_def}{I2\+C\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}hi2c)
\item 
\mbox{\hyperlink{group___h_a_l__mode__structure__definition_gabcbb7b844f2ffd63c4e530c117882062}{HAL\+\_\+\+I2\+C\+\_\+\+Mode\+Type\+Def}} {\bfseries HAL\+\_\+\+I2\+C\+\_\+\+Get\+Mode} (const \mbox{\hyperlink{struct_____i2_c___handle_type_def}{I2\+C\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}hi2c)
\item 
uint32\+\_\+t {\bfseries HAL\+\_\+\+I2\+C\+\_\+\+Get\+Error} (const \mbox{\hyperlink{struct_____i2_c___handle_type_def}{I2\+C\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}hi2c)
\end{DoxyCompactItemize}


\doxysubsection{Detailed Description}
Header file of I2C HAL module. 

\begin{DoxyAuthor}{Author}
MCD Application Team 
\end{DoxyAuthor}
\begin{DoxyAttention}{Attention}

\end{DoxyAttention}
Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-\/\+IS. 